The MODEL 601 pstage1 patch during fractal waveform processing

MODEL 601 Gen / RNBO

Rebuilding a programmable waveform instrument as portable DSP architecture

Project statement

Porting the behaviour, not only the signal flow

With MODEL 601 I am not translating a finished object into another language. I am trying to preserve the way its waveform can be touched, pushed and continuously transformed.

The current research starts from pstage1.maxpat, the principal patch in the Desktop GEN CODES archive. It gathers waveform reading, multiple processing stages, V-PRO, fractal indexing, spike, stretch, harmonics and wavefolding into an inspectable Gen-based structure. The immediate goal is to clarify and consolidate the DSP architecture; RNBO and hardware are the next porting targets, not a completed release.

Current environmentMax/MSP + Gen
Main patchpstage1.maxpat
Gen dependencies23 linked DSP modules
Next pathRNBO / hardware validation
Processing studies

The waveform under pressure

The complete Fractal study and three further local videos document central transformations from the same instrument research: fractal modulation, waveshape, spike and Buchla-inspired wavefolding.

WaveshapeContinuous movement between waveform families and intermediate timbral states.
SpikeAn audio-rate contour transformation focused on increasingly narrow waveform events.
Buchla WavefolderWavefolding research extending the oscillator through progressively folded spectra.
pstage1 anatomy

From waveform bank to portable DSP

The structure described here comes from the actual Max patch and its linked Gen files. It records the current architecture while keeping the RNBO and hardware stage explicitly prospective.

Waveform sources

Buffer-based sine, triangle, ramp, square, pulse and Gaussian or parabolic material enters the system through dedicated read-wave and ramp processors.

Parallel stage family

stage1 is accompanied by multiple named variants including nstage1, ostage1, ststage1, sestage1, cstage1, qstage1, tstage1, dstage1 and tnstage1. Their separation makes alternate processing paths visible during development.

V-PRO

vpro1, vpro2 and vprocalc define the continuous path from a central waveform toward two processed extremes, making intermediate states part of the instrument rather than transitional accidents.

Fractal motion

Fractal amplitude and speed are connected to a dedicated fractalindex stage. The process introduces nested motion into the waveform and is documented by the hero video.

Spike and stretch

spikecontrol and spikecalc work beside the stretch family to reshape waveform proportions at audio rate. Their interaction is central to the playable character of MODEL 601.

Harmonics and wavefolder

harmcalc, odd/even balance, symmetry controls, wavefolder2 and wfscaler connect geometric waveform change with harmonic and folded-spectrum control.

RNBO preparation

The next phase is to separate reusable DSP from Max-specific interface and routing, define stable parameter ranges, smooth continuous controls and validate equivalent behaviour before any hardware claim is made.

Artistic perspective
The interesting part of a port is deciding which relationships must remain alive when the surrounding technology changes.

MODEL 601 was conceived around continuous pressure between recognizable and unstable waveforms. For me, the Gen and RNBO path matters only if that tension survives: V-PRO must still feel like one gesture, fractal motion must remain structurally connected to the wave, and spike, stretch, harmonics and folding must continue to influence one another as parts of a single instrument body.

Validation path

Before the hardware port

Back to Max/MSP ->
  • Capture matched audio references from the existing pstage1 signal paths.
  • Verify every DSP stage at multiple sample rates and block sizes.
  • Smooth continuous parameters without weakening fast timbral gestures.
  • Keep DSP, interface and host or hardware integration clearly separated.
  • Check silence, impulse, sine, sweep, noise and extreme parameter settings.
  • Validate RNBO output on the selected target before describing hardware equivalence.